In the manufacture of large-area integrated circuit systems, it is relatively common for defects to occur in a small percentage of the elements that male up the integrated circuit system. In order to increase yields during the manufacture of the integrated circuit systems, redundant circuitry may be added that can be used to selectively replace defective primary circuit elements with secondary “backup” circuit elements. For example, in memory systems which may contain highly symmetric and repetitive device layouts, additional individual device elements, columns of elements, or rows of elements may be included in the circuit layout. These additional elements may be selectively activated through redundancy switches during the manufacturing process. Specifically, if during circuit testing a primary element is determined to be defective, a corresponding redundancy switch can be programmed to enable redundant circuitry to replace the functionality of the defective element. This type of testing is sometimes referred to as wafer sort, wafer sort test, wafer final test, electronic die sort and circuit probe.
Several types of redundancy switch elements are programmed via the selective blowing of integrated fuses located within the redundancy switch circuitry. These integrated fuses are ideally binary elements which act as resistive elements in their initial (default) state, and act as open circuits when blown. In practice, however, blown fuses may exhibit a certain amount of leakage current. In many cases, this leakage current may manifest in relatively benign consequences, such as slight increases in power consumption by the redundancy switch. However, depending on the switch circuitry configurations, this leakage current also may result in the failure of the redundancy switch to function properly. This problem has become more prevalent as device dimensions have shrunk, resulting in increased leakage currents.
FIG. 1 shows a conventional switch control circuit 100 that is programmed through the use of two integrated fuses 106 and 108. The switch control circuit 100 takes as input the reference voltages VDD 120 and VSS (ground) 122, and outputs an enable signal 102 and its complement 104. In its default state, fuses 106 and 108 are not blown, and act as resistive elements. As a result, internal node N1 114 is resistively coupled to VSS 122 and internal node N2 110 is resistively coupled to VDD 120. When reference voltage VDD 120 is powered up, N2 110 rises to the voltage level of VDD. Because N2 110 is coupled to the gate input of p-type transistor MP2 112, as the voltage level of VDD rises, N2 110 maintains MP2 112 in the “off” position. Additionally, although N1 114 is capacitively coupled to VDD through the gate capacitance of p-type transistor MP1 118, the resistive coupling of node N1 114 to VSS 122 through fuse F1 108 is sufficient to maintain N1 114 at VSS. N-type transistor MN1 116 is also maintained in the “off” position while N1 114 is maintained at VSS.
In the programmed position, the integrated fuses 106 and 108 are blown and ideally act as open circuits. In this configuration, node N1 114 is no longer resistively coupled to VSS 122 and the capacitive coupling with VDD 120 through MP1 118 eventually pulls N1 114 up to VDD. This rise in voltage of N1 114 is sufficient to turn on transistor MN1 116 and set node N2 110 to VSS. With N2 110 tied to VSS 122, transistor MP2 112 is turned on, thereby reinforcing the voltage of N1 114 at VDD. With N1 114 set to VDD, the output enable signal 102 is set to VDD and its complement 104 is set to VSS.
However, as noted above, fuses do not act as ideal open circuits when blown and instead may present a source of leakage current. Thus, when switch control circuit 100 is in the programmed position and fuses 106 and 108 are blown, node N1 114 is not entirely de-coupled from node VSS 122 and leakage current may flow from N1 114 through fuse 108 to reference voltage VSS 122. Moreover, if blown fuse 108 provides too much leakage current, node N1 114 may not be pulled up to VDD through the capacitive coupling of MP1 118. In this case, N1 114 is maintained at VSS and the output signals 102 and 104 are placed in the incorrect state. This condition is more pronounced when the power-on ramp rate of VDD is slower, since leakage current through blown fuse 108 is provided a greater opportunity to drain charge provided to N1 114 through capacitive coupling to VDD.
Thus, there exists the possibility that existing switch control circuits may operate incorrectly in certain situations, especially when blown fuses provide relatively large amounts of leakage current or when power-on ramp rates of reference voltages are relatively slow. Therefore, it would be beneficial to have a system or circuit that was more resistant to the conditions presented by these situations.